d a t a sh eet product speci?cation supersedes data of december 1990 file under integrated circuits, ic06 1997 nov 25 integrated circuits 74hc/hct109 dual j k flip-flop with set and reset; positive-edge trigger for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
1997 nov 25 2 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 features j, k inputs for easy d-type flip-flop toggle flip-flop or do nothing mode output capability: standard i cc category: flip-flops general description the 74hc/hct109 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct109 are dual positive-edge triggered, j k flip-flops with individual j, k inputs, clock (cp) inputs, set ( s d ) and reset ( r d ) inputs; also complementary q and q outputs. the set and reset are asynchronous active low inputs and operate independently of the clock input. the j and k inputs control the state changes of the flip-flops as described in the mode select function table. the j and k inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. the j k design allows operation as a d-type flip-flop by tying the j and k inputs together. schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. quick reference data gnd = 0 v; t amb = 25 c; t r = t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v. ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay c l = 15 pf; v cc = 5 v ncp to nq, n q1517ns n s d to nq, n q1214ns n r d to nq, n q1215ns f max maximum clock frequency 75 61 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per ?ip-?op notes 1 and 2 20 22 pf
1997 nov 25 3 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 pin description pin no. symbol name and function 1, 15 1 r d , 2 r d asynchronous reset-direct input (active low) 2, 14, 3, 13 1j, 2j, 1 k, 2 k synchronous inputs; ?ip-?ops 1 and 2 4, 12 1cp, 2cp clock input (low-to-high, edge-triggered) 5, 11 1 s d , 2 s d asynchronous set-direct input (active low) 6, 10 1q, 2q true ?ip-?op outputs 7, 9 1 q, 2 q complement ?ip-?op outputs 8 gnd ground (0 v) 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
1997 nov 25 4 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 fig.4 functional diagram. function table notes 1. h = high voltage level h = high voltage level one set-up time prior to the low-to-high cp transition l = low voltage level i = low voltage level one set-up time prior to the low-to-high cp transition q = lower case letters indicate the state of the referenced output one set-up time prior to the low-to-high cp transition x = dont care - = low-to-high cp transition operating mode inputs outputs s d r d cp j kq q asynchronous set l h x x x h l asynchronous reset h l x x x l h undetermined l l x x x h h toggle h h - hl qq load 0 (reset) h h - ll l h load 1 (set) h h - hh h l hold no change h h - lh q q package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.5 logic diagram (one flip-flop). handbook, full pagewidth mbk217 c c c c c k j cp s r c c c c c q q
1997 nov 25 5 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: flip-flops ac characteristics for 74hc gnd = 0 v; t r = t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) test conditions 74hc unit v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay ncp to nq, n q 50 18 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.6 t plh propagation delay n s d to nq 30 11 9 120 24 20 150 30 26 180 36 31 ns 2.0 4.5 6.0 fig.7 t phl propagation delay n s d to n q 41 15 12 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 fig.7 t phl propagation delay n r d to nq 41 15 12 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 fig.7 t plh propagation delay n r d to n q 39 14 11 170 34 29 215 43 37 255 51 43 ns 2.0 4.5 6.0 fig.7 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.6 t w clock pulse width high or low 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.6 t w set or reset pulse width high or low 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.7 t rem removal time n s d ,n r d to ncp 70 14 12 19 7 6 90 18 15 105 21 18 ns 2.0 4.5 6.0 fig.7 t su set-up time nj, n k to ncp 70 14 12 17 6 5 90 18 15 105 21 18 ns 2.0 4.5 6.0 fig.6 t h hold time nj, n k to ncp 5 5 5 0 0 0 5 5 5 5 5 5 ns 2.0 4.5 6.0 fig.6 f max maximum clock pulse frequency 6.0 30 35 22 68 81 5.0 24 28 4.0 20 24 mhz 2.0 4.5 6.0 fig.6
1997 nov 25 6 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: flip-flops ac characteristics for 74hct gnd = 0 v; t r = t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay ncp to nq, n q 20 35 44 53 ns 4.5 fig.6 t plh propagation delay n s d to nq 13 26 33 39 ns 4.5 fig.7 t phl propagation delay n s d to n q 19 35 44 53 ns 4.5 fig.7 t phl propagation delay n r d to nq 19 35 44 53 ns 4.5 fig.7 t plh propagation delay n r d to n q 16 32 40 48 ns 4.5 fig.7 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.6 t w clock pulse width high or low 18 9 23 27 ns 4.5 fig.6 t w set or reset pulse width high or low 16 8 20 24 ns 4.5 fig.7 t rem removal time n s d , n r d to ncp 16 8 20 24 ns 4.5 fig.7 t su set-up time nj, n k to ncp 18 8 23 27 ns 4.5 fig.6 t h hold time nj, n k to ncp 3 - 3 3 3 ns 4.5 fig.6 f max maximum clock pulse frequency 27 55 22 18 mhz 4.5 fig.6
1997 nov 25 7 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 ac waveforms fig.6 waveforms showing the clock (ncp) to output (nq, n q) propagation delays, the clock pulse width, the nj, n k to ncp set-up, the ncp to nj, n k hold times, the output transition times and the maximum clock pulse frequency. the shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth mbk216 v m (1) ncp input ns d input nr d input nq output nq output v m (1) v m (1) v m (1) v m (1) t w t rem t rem t w t phl t plh t plh t phl fig.7 waveforms showing the set (n s d ) and reset (n r d ) input to output (nq, n q) propagation delays, the set and reset pulse widths and the n r d , n s d to ncp removal time. (1) hc: v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
1997 nov 25 8 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so, ssop and tssop r eflow soldering reflow soldering techniques are suitable for all so, ssop and tssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering can be used for all so packages. wave soldering is not recommended for ssop and tssop packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering is used - and cannot be avoided for ssop and tssop packages - the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions: only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1). do not consider wave soldering tssop packages with 48 leads or more, that is tssop48 (sot362-1) and tssop56 (sot364-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 nov 25 9 philips semiconductors product speci?cation dual j k ?ip-?op with set and reset; positive-edge trigger 74hc/hct109 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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